The desire for higher performance circuits has driven the development of high-speed sub-100 nanometer (nm) silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology. In SOI technology, transistors are formed on a thin layer of silicon overlying a layer of insulating material. Devices formed on SOI offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.
U.S. Pat. No. 5,952,695 to Ellis-Monaghan et al. discloses silicon-on-insulator and CMOS-on-SOI double film structures. Electrostatic discharge (ESD) characteristics of the SOI device is improved by having a thick double layer of silicon in selected regions.
U.S. Pat. No. 6,222,234 B1 to Imai discloses a semiconductor device with a fully-depleted SOI MOSFET and a partially-depleted SOI MOSFET on the same SOI substrate through isolation by an element isolation film.
U.S. Pat. Nos. 6,414,355 B1 and 6,448,114 B1 both to An et al. disclose, respectively, a silicon-on-insulator chip having an active layer of non-uniform thickness and a method of fabricating same.
U.S. Pat. No. 6,096,584 to Ellis-Monaghan et al. describes a silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region.
U.S. Pat. No. 6,399,989 to Dockerty et al. describes a radiation hardened silicon-on-insulator transistor.
The article entitled “Ultra-Thin Body PMOSFET's with Selectively Deposited Ge Source/Drain;” Yang-Kyu Choi et al.; 2001 Symposium on VLSI Technology Digest of Technical Papers held Jun. 12 to 14, 2001 in Kyoto Japan; pages 19 and 20; describes ultra-thin body MOSFETs with body thicknesses down to 4 μm and selectively deposited germanium (Ge) raised source and drains.
The article entitled “A 50 nm Depleted-Substrate CMOS Transistor (DST);” Robert Chau et al.; International Electron Device Meeting 2001 held Dec. 2 to 5, 2001 in Washington, D.C., pages 621 to 624; describes depleted-substrate transistor (DST) technology wherein depleted-substrate CMOS transistors were fabricated on thin silicon body (≦30 nm) with physical gate lengths down to 50 nm which show steeper subthreshold slopes (≦75 mV/decade) and improved DIBL (≦50 mV/V) over both partially-depleted (P-D) SOI and bulk Si, for both PMOS and NMOS transistors.